1. Field of the Invention
The present invention relates to a graphic processor and a graphic processing method to process figures to be displayed on a display unit by use of a microcomputer, and particularly relates to a graphic processor and a graphic processing method suitable for a system to rapidly display a plurality of figures in motion with three-dimensionally overlaying them.
2. Description of the Related Art
Recently, various special functions are required for pictures displayed on a graphic display unit so as to improve the effect appealing to the viewers' perception. One of such special functions is the stereoscopic display. It is an expression technique to display a three-dimensional scene with a depth having a plurality of mutually overlaid figures (sprites) in rapid motion and change on the screen of a graphic display unit.
Referring to FIGS. 4, 5 and 6, a conventional graphic processor and a graphic processing method used for stereographic display are described below. FIG. 4 shows a stereoscopic display screen displaying a first figure G1 comprising 4*4 pixels at the coordinates (40, m) and a second different figure G2 comprising 4*4 pixels at the coordinates (42, n) on the first line of a display screen SC1 with the second figure G2 displayed in front of the first figure G1. FIG. 5 is a block diagram illustrating the configuration of a graphic processor and the signal flow and FIG. 6 is a timing chart of the signal waveforms when the figures in FIG. 4 are displayed.
As shown in FIG. 5, a conventional graphic processor 20 comprises a drawing processor 21, a timing generator 22 and a display buffer 23 and outputs the graphic display data to a display 24 as a graphic display unit. The timing generator 22 has input of the clock signal (S1), the vertical sync signal (S3) and the horizontal sync signal (S2) and outputs the drawing processor control signal (S4), the display initialize signal (S8) and the drawing display switching signal (S11). The drawing processor 21 incorporates a storage to store the original data of the displayed figure. It receives the input of the clock signal (S1), the drawing processor control signal (S4) and the display initialize signal (S8) for certain drawing processing and outputs graphic data comprising the drawing graphic data signal (S5), the display buffer write enable signal (S6) and the display buffer drawing address signal (S7). The display buffer 23 temporarily stores the graphic data and outputs the graphic display data to the display 24 in response to input of the drawing display switching signal (S11).
Next, referring to FIG. 6, the operation of the graphic processor 20 when displaying the first line as shown in FIG. 4 is described below.
Firstly, at the same time as the activation of the graphic processor 20, the vertical sync signal (S2) is input from the main system (not shown) to the graphic processor 20 and the timing generator 22 is initialized. Note that rewriting of the whole contents in the display buffer to the graphic data to display the same color as the screen background color (i.e. no display on the screen) is referred to as the display initialization in the description below. The graphic data to display the same color as the screen background color is called the transparent data. In other words, the transparent data is the graphic data of the same color as that of the screen background so that it causes nothing to be displayed on the screen. The background color is usually specified by the user.
Next, prior to the operation to display figures on the screen updated periodically, the graphic processor 20 is initialized for every update of the screen. For this, once for every update of the screen, the horizontal sync signal (S3) is input from the main system (not shown) to the timing generator 22. Upon input of the horizontal sync signal (S3), the drawing processor control signal (S4), the display initialize signal (S8) and the drawing display switching signal (S11) are output from the timing generator 22.
The drawing processor 21 is initialized by the display initialize signal (S8) and then the display buffer 23 is initialized by the display initialize signal from the drawing processor 21. These processes bring the graphic processor 20 to the drawing start status.
Referring to FIG. 6, initialization of the graphic processor 20 starts when the drawing display switching signal (S11) reaches the low level (hereinafter indicated as "0" (L)) and is executed while the display initialize signal (S8) is at "0" (L). Corresponding to the display buffer drawing address signal (S7)="0" to "n" (number of display buffers), transparent data is provided as the drawing graphic data signal (S5). Meanwhile, in response to the display buffer drawing address signal (S7), the display buffer write enable signal (S6) becomes "0" (L). Thus, by replacing the data at the addresses used for display in the display buffer 23 entirely with transparent data, initialization of the display buffer 23 is completed.
Upon completion of initialization of the display buffer 23, the display initialize signal (S8) rises to the high level (hereinafter indicated as "1" (H)) and terminates the initialization process of the graphic processor 20. Then, the graphic processor 20 is in the drawing start status, where graphic data can be stored to the display buffer 23.
The drawing processor 21 firstly displays the figure G1 with a low display priority as shown in FIG. 4. For this, it serially outputs, as the graphic data, the display buffer drawing address signal (S7)="40" to "43" (h) and the corresponding drawing graphic data signal (S5) for every clock signal (S1). During this period, corresponding to the display buffer drawing address signal (S7), the display buffer write enable signal (S6) becomes "0" (L) and the drawing graphic data signal (S5), the display buffer write enable signal (S6) and the display buffer drawing address signal (S7) are stored to the display buffer 23 as the graphic data of the figure G1.
Then, the drawing processor 21 displays the figure G2 as shown in FIG. 4. For this, it serially outputs, as the graphic data, the display buffer drawing address signal (S7)="42" to "45" (h) and the corresponding drawing graphic data signal (S5) for every clock signal (S1). During this period, corresponding to the display buffer drawing address signal (S7), the display buffer write enable signal (S6) becomes "0" (L) and the drawing graphic data signal (S5), the display buffer write enable signal (S6) and the display buffer drawing address signal (S7) are stored to the display buffer 23 as the graphic data of the figure G2.
Upon completion of operation to store the graphic data for drawing to the display buffer 23, the drawing display switching signal (S11) becomes "1" (H) and the graphic processor 20 moves to the graphic display status. Then, the graphic processor 20 reads out the graphic data from the display buffer 23 and starts its output as the graphic display data signal. After moving to the graphic display status, the drawing processor 21 provides the display buffer 23 with the display buffer drawing address signal (S7)="0" to "n". Thus, the corresponding display data signal (S9) is taken out from the display buffer 23 and output to the display 24. By these processes above, the figures G1 and G2 are displayed on the display screen as shown in FIG. 4.
Then, referring to FIGS. 4, 7, 8 and 9, another example of the conventional graphic processor is described below. FIG. 7 is a block diagram to illustrate the configuration of a graphic processor and the signal flow, FIG. 8 is a block diagram to show the configuration of a status register and FIG. 9 is a timing chart of the signal waveforms when the figures in FIG. 4 are displayed.
As shown in FIG. 7, a graphic processor 30 is provided with, in addition to the drawing processor 21, the timing generator 22 and the display buffer 23, a status register 31 to determine the display priority and output the mask signal (S13) when storing the display data to the display buffer 23 and a mask section 32 which, in response to the mask signal (S13), masks the display buffer write enable signal (S6) and outputs the post-masking display buffer write enable signal (S15).
Next, referring to FIG. 9, the operation of the graphic processor 30 when displaying the first line in FIG. 4 is described.
Firstly, at the same time as the activation of the graphic processor 30, the vertical sync signal (S2) is input from the main system (not shown) to the graphic processor 30 and the timing generator 22 is initialized. Then, the horizontal sync signal (S3) is once input from the main system (not shown) to the timing generator 22. Upon input of the horizontal sync signal (S3), the drawing processor control signal (S4), the display initialize signal (S8) and the drawing display switching signal (S11) are output from the timing generator 22. The drawing processor 21 is initialized by the display initialize signal (S8) and then the display buffer 23 is initialized by the display initialize signal from the drawing processor 21.
Referring to FIG. 9, initialization of the graphic processor 30 starts when the drawing display switching signal (S11) reaches "0" (L) and is executed while the display initialize signal (S8) is at "0" (L). Corresponding to the display buffer drawing address signal (S7)="0" to "n" (number of display buffers), transparent data is provided as the drawing graphic data signal (S5). Meanwhile, in response to the display buffer drawing address signal (S7), the display buffer write enable signal (S6) becomes "0" (L). Thus, by replacing the data at the addresses used for display in the display buffer 23 entirely with transparent data, initialization of the display buffer 23 is completed. The status register 31 is also initialized by the display initialize signal (S8) from the timing generator 22.
Upon completion of initialization of the display buffer 23, the display initialize signal (S8) rises to "1" (H)) and terminates the initialization process of the graphic processor 30, which enters the drawing start status.
The status register 31 is, as shown in FIG. 8, provided with an encoder 311, two-input OR gates 312 for the same number of addresses as that of the display buffer 23, two-input AND gates 313 for the same number of addresses as that of the display buffer 23, registers 314 for the same number of addresses as that of the display buffer 23 and a selector 315 to select one of the signals output from the register B11.
With the above configuration, the status register 31 has its all addresses in the register 314 reset during initialization and has the data corresponding to the accessed arbitrary addresses in the register 314 set during operation other than initialization. The register 314 is set by input of "1" (H) signal and reset by input of "0" (L) signal.
Firstly, the drawing processor 21 serially outputs, as the graphic data to draw the figure G2 shown in FIG. 4, the display buffer drawing address signal (S7)="42" to "45" (h) and corresponding drawing graphic data signal (S5) for every clock signal (S1). During this period, corresponding to the display buffer drawing address signal (S7), the display buffer write enable signal (S6) becomes "0" (L).
The status register 31 outputs, upon receipt of the display buffer drawing address signal (S7)="42" to "45" (h), the mask signal (S13)="0" (L) for this period. Its internal status is set so that "1" (H) is output as the mask signal (S13) when the display buffer drawing address signal (S7)="42" to "45" (h) is input for the next time.
The mask section 32 masks the display buffer write enable signal (S6) when the mask signal (S13)="1" (H) and does not mask the display buffer write enable signal (S6) when the mask signal (S13)="0" (L) for output. In other words, when the mask signal (S13)="0" (L) is received, the display buffer write enable signal (S6) is output without any change as the post-masking display buffer write enable signal (S15). The display buffer 23 stores, as the graphic data of the figure G2, the drawing graphic data signal (S5), the display buffer drawing address signal (S7) and the post-masking display buffer write enable signal (S15).
Subsequently, the drawing processor 21 serially outputs, as the graphic data to draw the figure G1 as shown in FIG. 4, the display buffer drawing address signal (S7)="40" to "43" (h) and the corresponding drawing graphic data signal (S5) for every clock signal (S1). During this period, the display buffer write enable signal (S6) becomes "0" (L) corresponding to the display buffer drawing address signal (S7).
As described above, the status register 31 has its internal status set so that it outputs the mask signal (S13)="0" (L) upon input of the display buffer drawing address signal (S7)="40" to "41" (h) and outputs "1" (H) upon input of the display buffer drawing address signal (S7)="42" to "43" (h). Thus, upon receipt of the display buffer drawing address signal (S7)="40" to "43" (h), the status register 31 outputs the mask signal (S13)="0" (L) while the display buffer drawing address signal (S7)="40" to "41" and outputs the mask signal (S13)="1" (H) while the display buffer drawing address signal (S7)="42" to "43".
While the display buffer drawing address signal (S7)="40" to "41", the mask section 32 accepts the mask signal (S13)="0" (L) and outputs the display buffer write enable signal (S6) without any change as the post-masking display buffer write enable signal (S15). While the display buffer drawing address signal (S7)="42" to "43", it receives the mask signal (S13)="1" (H), masks the display buffer write enable signal (S6) and outputs the post-masking display buffer write enable signal (S15)="1" (H). The display buffer 23 stores, as the graphic data of the figure G1, the drawing graphic data signal (S5), the display buffer drawing address signal (S7), and the post-masking display buffer write enable signal (S15).
Upon completion of operation to store the graphic data for drawing to the display buffer 23, the drawing display switching signal (S11) becomes "1" (H) and the graphic processor 30 moves to the graphic display status. Then, the drawing processor 21 provides the display buffer 23 with the display buffer drawing address signal (S7)="0" to "n". Thus, the corresponding display data signal (S9) is taken out from the display buffer 23 and output to the display 24. By these processes above, the figures G1 and G2 are displayed on the display screen as shown in FIG. 4.
Referring to FIG. 10 now, the reason why the display initialization is required for every update of the screen in operation of the graphic processor is explained.
Suppose, for example, a screen SC2 containing a figure G3 is displayed on the display screen of the display 24 as shown in FIG. 10(a). When the screen SC2 is updated and the screen SC3 containing a figure G4 as shown in FIG. 10(b) is displayed, display of the figure G4 immediately after the status of screen SC2 causes the figure G3 on the previous screen SC2 to be displayed in the area without any data on the screen SC3 as shown in FIG. 10(c).
To prevent such situation in update of the screen SC2, the contents of the display buffer are entirely replaced with graphic data for no display or transparent data by the display initialization process before display of the screen SC3. Thus, as shown in FIG. 10(b), the figure G4 only can be properly displayed on the screen SC3.
The conventional graphic processor as described above writes transparent data to the display buffer during display initialization. Graphic data cannot be stored to the display buffer during this process, which results in a lower throughput and graphic display capacity of the graphic processor. However, it was not considered as a drawback because the time required for display initialization was short in conventional systems.
Recently, improved resolution of display increases the amount of graphic data to be displayed on the screen and results in a longer time required for display initialization. For this reason, deterioration of the throughput and graphic display capacity of the graphic processor becomes too grave to ignore.
Further, only a small number of figures were displayed and the user had enough time to execute graphic processing after display initialization before. At present, displayed figures become complicated and sophisticated with the progress in display resolution and the time for graphic processing becomes insufficient.